The present invention relates to a data generator suitable for generating fast serial data having arbitrary data length.
There are various ways to inspect an electronic circuit to determine if the circuit is operating properly. One way is to provide a test digital data pattern to a circuit under test and to verify that the output of the circuit is as expected. In this case, a desired digital data pattern is stored in a memory and provided to a data generator which generates the corresponding data pattern signal. Another way is to provide an arbitrary analog signal to the circuit under test wherein the digital data corresponding to the analog signal is prepared in advance and an digital-to-analog converter converts the digital data into the analog signal. In these and other examples, a digital data pattern is necessary. U.S. Pat. No. 6,032,275 by Masaru, for example, discloses such data generation and measurement of a circuit under test.
FIG. 1 shows an example of a parallel data generator 10 having a memory for storing digital data patterns. A selected digital data pattern is read from the memory but the reading speed is not sufficiently fast so the data is read in parallel from the memory by a given bit width and then converted into serial data to have a desired data speed. The parallel data generator 10 provides parallel data according to a divided clock DCLK and a parallel to serial converter 12 converts the parallel data into serial data according to a reference clock RCLK. In this example, the bit width of the parallel data is four bits. The parallel to serial converter 12 receives and divides the reference clock RCLK by four to produce and provide the divided clock DCLK to the data generator 10.
In case of FIG. 1, the length of the data pattern is limited to multiples of four bits. However, it is desirable to be able to generate data patterns having arbitrary lengths. FIG. 2 shows another data generator that produces a data pattern having an arbitrary length. A parallel data generator 14 selectively provides parallel data having four or five effective bits and a bit width identifier BWI. A parallel to serial converter 16 receives the bit width identifier BWI to control the bit width in the parallel to serial conversion at one time so that it converts the parallel data of four or five bit width into serial data according to a reference clock RCLK. Wherein the frequency of the reference clock RCLK is constant but the frequency of a divided clock DCLK changes according the bit width of the first parallel data converted by the converter 16.
Phase lock loop (PLL) and/or delayed lock loop (DLL) are well known technique to realize a fast logic circuit. The DLL intentionally delays clock phase up to maximum one clock as if there were no clock delay. The frequency of the divided clock DCLK in FIG. 2 changes depending on the bit width in the parallel to serial conversion, which produces noise. Therefore, PLL or DLL cannot be used, which prevents the data generator from working fast.